In central processing unit (CPU) chips, parts of the circuit are generally put down by power gating techniques when not operated to save power. Under current technology, high threshold voltage field effect transistors (FETs) are used for the power gating. It has been found, in practice, that a considerable amount of power is wasted due to voltage drop on BEOL wiring between power gating transistors and the shut down circuit.
In accordance with the present invention, MEMS transistors are constructed in the far back end of line (FBEOL) for use instead of transistors, such as standard FETs, which cannot be built at BEOL, and can only be built at the front end of line (FEOL).